1. Field of the Invention
The present invention relates to a simulation execution apparatus for executing simulation of a logic circuit model expressed in a hardware description language or the like, and a method and a computer readable medium storing program therefor.
2. Related Art
Recently, in design and manufacture of a large-scale logic circuit such as LSI (large-scale integration), it is common that hardware is described in a language called a hardware description language (HDL) to manufacture actual hardware such as LSI from the written HDL.
Meanwhile, recently, in embedded devices for mobile phones and the like, software is more and more larger-scaled while the development cycle is shorter and shorter, so that the speed of development and tests cannot keep up with the situation. Therefore, the importance of simulation execution of an HDL, which enables efficient logic verification and evaluation to be done before manufacture of hardware, is increasing.
As the HDL, for example, Verilog HDL, VHDL and the like are often used. There may be a case where, in order to execute simulation of the HDL, an equivalent code (for example, a C code) is manually created by a man. Because a man can understand the intention of specifications and HDL, a high-speed code suitable for simulation execution may be created.
As a tool for automatically performing simulation execution, tools such as iverilog, verilator and NC-verilog for Verilog HDL are known. Basically, these simulation execution tools faithfully execute the circuit operation expressed in an HDL along a time axis. However, a logic circuit is commonly designed and described on the assumption of parallelism and a small storage area. Therefore, in the case of performing faithful simulation execution in an environment with an operation part with low parallelism and a large storage area, such as a PC (personal computer), the processing tends to be redundant and wasteful.
Therefore, various means have been devised in order to increase the speed of simulation execution. For example, JP-A 2005-321848 (Kokai) discloses a method for speed-up in which static analysis of an HDL is performed before simulation execution to delete unnecessary description. In verilator described above, it is possible to, by converting an HDL to an equivalent C code once, utilize optimization by a compiler. As a method for semi-automation, a method is also known in which the bottleneck part of simulation execution time is automatically identified and is edited by a man to increase the execution speed, as seen in NC-verilog described above.
When simulation execution of a logic circuit described in an HDL is performed, all of the following three viewpoints are important: accuracy of the operation of simulation execution, time and effort required for creation, and execution speed.
In the case of a man manually creating an execution code and the case of semi-automatically creating an execution code, as described above, it is possible to create a high-speed execution code if the creator is sufficiently skilled. However, much time and effort is required, and there is a possibility that the operation may be inaccurate because creation is manually performed.
On the other hand, in the case of automatically creating a simulation execution code, the accuracy of simulation execution is ensured, and the time and effort required for creation is little in many cases. However, it is difficult to increase the execution speed.
As one of the causes of the difficulty of increasing the execution speed, in the existing methods such as iverilog and verilator, it is given that execution time is wastefully consumed because simulation execution of actual circuit operation is faithfully performed, and a repeated operation is also faithfully executed.
In JP-A 2005-321848 (Kokai) described above, a method for detecting the cyclicity of circuit operation by static analysis is described. However, it is necessary to register a cycling pattern in advance, which requires much time and effort.
As described above, there is still room for improvement of the method for performing simulation execution at a high speed.